Analisis Kinerja Multistage Interconnection Network Topologi Gamma Berukuran 16X16

Abstract

The development of switching technology has increasingly attracted significant attention in recent years. In the field of telecommunications, the rapid growth in the number of subscribers and the diversity of information demand high-speed switching with large capacity. In the field of computing, in order to achieve effective parallel computation, an interconnection network that is reliable, efficient, and capable of handling high-speed data transfer is required. One of the solutions employed is the use of Multistage Interconnection Networks (MIN). This study analyzes the performance of a Gamma topology MIN with a 16×16 configuration, designed to minimize internal blocking through the implementation of a routing algorithm based on routing tags. The analysis was conducted on key parameters, namely throughput, blocking probability, and transfer delay. The Gamma network simulation was carried out using the Python programming language with five random permutation patterns as the test scenarios. The results show that the 16×16 Gamma Network is capable of achieving a non-blocking condition in all tested permutations, yielding a throughput of 100% and a blocking probability of 0%. With a switching speed of 1 Gbps, the obtained transfer delay values are relatively low: for PCM-24 the delay is 0.96 μs, for PCM-30 the delay is 1.28 μs, for T3/E3 the delay is 2.56 μs, and for Ethernet/IP the delay is 5.12 μs. This study reinforces the potential of the Gamma topology to be adopted as a reliable high-speed interconnection network solution for large-scale applications in the fields of telecommunications and computing.